1. Field of the Invention
This invention relates to data handling systems having a driven output signal line.
2. Description of the Prior Art
Various known data handling apparatus and methods, such as microprocessors, memories and communications devices, have a need to drive output signal lines. It is known for performance and protection reasons to provide buffer stages between the output signal lines being driven and the circuitry generating the data signals to be output.
FIG. 1 of the accompanying drawings illustrates a data handling device 2 having a simple, conventional output signal driving circuit 4 driving a plurality of output signal lines 6 on an output bus 8. The output signal driving circuit 4 includes a functional block 10, such as a random access memory block, that serves to generate data signals on data lines 12 for output via the output bus 8.
The functional block 10 generates the data signals in response to various input signals (input1, input2). The functional block 10 is selected and enabled via an enable signal (in this case also serving as a select signal) on an enable line 14 that also passes (via an enable input "e") to each of a plurality of buffers 16 that are provided for the data signal lines 12. The buffers 16 serve to isolate the functional block 10 from the output bus 8 and provide a degree of power amplification for driving the relatively high capacitance output bus 8.
FIG. 2 of the accompanying drawings shows a timing diagram for various signals within the data handling device 2 of FIG. 1. The "select" signal switches state to enable the upper output signal driving circuit 4 of FIG. 1. This "select" signal enables the functional block 10 and the buffers 16. The output of the functional block 10 (FB1 Output) takes a finite amount of time to settle to its eventual data signal value. During this time spurious signals ("glitches,") are placed upon the data signal lines 12. Since the buffer circuits 16 are enabled by the "select" signal, this has moved them from a high impedance state to an active state and thus they serve to power amplify the spurious signals on the data signal lines 12 and pass this onto the output bus 8. Driving the output bus 8, which is of a relatively high capacitance, with spurious, rapidly changing signals via the output buffers 16 consumes a significant amount of circuit power. Furthermore, the circuitry elsewhere that is connected to the output bus 8 must be protected from the spurious signals that are temporarily present on the output bus 8.
FIG. 3 of the accompanying drawings illustrates an alternative arrangement to that of FIG. 1 (as used in the ARM600 integrated circuit produced by Advanced RISC Machines Limited) in which latching circuits 18 have been interposed between the functional block 10 and the buffers 16. The functional block 10 has an additional data valid output (dv) that is asserted when the data signals from the functional block 10 have settled to valid values. The data valid signal triggers the latching circuits 18 to latch the values input to the latching circuits. These latched values are then passed to the buffers 16.
FIG. 4 of the accompanying drawings illustrates a timing diagram for the circuit of FIG. 3 similar to that illustrated in FIG. 2. In this case, since the outputs of the functional block 10 are latched by the latching circuits 18, the data signals need only be asserted by the functional block 10 long enough for them to be latched by the latching circuits 18. Once the data signals are latched, the functional block 10 can resume a quiescent state in which it consumes less power. This circuit does not deal with the problem of spurious signals being output on the output bus 8.
FIG. 5 of the accompanying drawings illustrates a possible modification of the circuit of FIG. 3. In this case, the buffers 16 are not enabled by the "select" signal. Instead, the data valid signal is used to enable the buffers 16, the data valid signal passing through an enable latch 20. The enable latch 20 preserves the enable signal to the buffers 16 even when the functional block 10 returns to its quiescent state.
FIG. 6 of the accompanying drawings illustrates the timing of various signals within the circuit of FIG. 5. In this case, since the buffers 16 are not enabled until the data valid signal is asserted, no spurious signals are input to or output from the buffers 16. However, this arrangement has the disadvantage that a finite time (T) is needed between the data valid signal being applied to the buffers 16 and the buffers 16 being able to drive the output bus 8. The extra time delay this introduces is a performance disadvantage, e.g. an increase in memory access time.